`timescale 1ns / 1ps
`include "defines.v"
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/09 14:45:43
// Design Name: 
// Module Name: ps_reg
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module pc_reg(
    input wire clk,
    input wire rst,
    output reg[`InstAddrBus] pc,  //要读取的指令地址
    output reg ce  //指令存储器使能
    );

    always @(posedge clk) begin
        if (rst == `RstEnable) begin
            ce <= `ChipDisable; //复位的时候指令存储器禁用
        end
        else begin
            ce <= `ChipEnable;
        end
    end

    always @(posedge clk) begin
        if (ce == `ChipDisable) begin
            pc <= `ZeroWord;
        end else begin
            pc <= pc + 4'h4; //一条指令的长度是32位，故而需要+4
        end
    end

endmodule
